1. Field of the Invention
The present invention relates to semiconductor fabrication.
2. Description of the Related Art
In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on semiconductor wafers. The semiconductor wafers include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
The series of manufacturing operations for defining features on the semiconductor wafers can include an electroplating process for adding material to the surface of the semiconductor wafer. Conventionally, electroplating is performed in a complete wafer electroplating processor with the entire wafer submerged in an electrolyte. During the conventional electroplating process, the wafer is maintained at a negative potential with respect to a positively charged anode plate, wherein the anode plate is substantially equal in size to the wafer. The anode plate is also submerged in the electrolyte and maintained in a position proximate to and parallel with the wafer.
During the plating process the wafer acts as a cathode. Thus, the wafer is required to be electrically connected to a number of electrodes. The number of electrodes are required to be uniformly distributed around a perimeter of the wafer and have substantially matched contact resistances in order to achieve a uniform current distribution across the wafer. In the complete wafer electroplating processor, a non-uniform current distribution across the wafer can result in a non-uniform plating thickness across the wafer.
While the conventional complete wafer electroplating processor is capable of depositing material on the surface of the wafer, there is an ever present need to continue researching and developing improvements in electroplating technology applicable to material deposition during semiconductor wafer fabrication.